verilog 中 wire与 reg区别

1.There are two main groups of data types: the register data types and the net data types.

The net data types represent physical connections between structural entities,
such as gates. A net does not store a value (except for the trireg net).

A register is an abstraction of a data storage element.
A register stores a value from one assignment to the next.
An assignment statement in a procedure acts as a trigger that changes the value in the data storage element.
The default initialization value for a reg data type is the unknown value, x.

2.verilog-2001中的描述
wire：
A wire net can be used for nets that are driven by a single gate or continuous assignment.
reg：
Assignments to a reg are made by procedural assignments (see 6.2 and 9.2). Since the reg holds a value between assignments, it can be used to model hardware registers. Edge-sensitive (i.e., flip-flops) and level sensitive (i.e., RS and transparent latches) storage elements can be modeled. A reg needs not represent a hardware storage element since it can also be used to represent combinatorial logic.


3. 其实是不同的抽象级别，wire 如同vhdl中的signal类型，是和实际的物理连接对应的，而reg属于算法描述层次用的类型，和实际电路没有直接的对应关系，也就是说它相当于c语言中的变量（int，float等），vhdl中的variable。记住这句就可以了，reg不和实际的电路如寄存器对应，高层次的描述时用。
always其实算是算法级描述的语句，所以其中的变量必须声明为reg，还有initial。